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【分享】 芯来e203移植开发分享(一)——vcs+verdi仿真环境搭建

发表于 全国大学生集成电路创新创业大赛 2022-03-07 13:29:36
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报名编号:CICC2520 团队名称:暗物质队

简单介绍

这里就不详细介绍蜂鸟e203,e203的仿真环境使用的是iverilog,一般工作中,主要使用的是vcs+verdi。个人觉得使用vcs的学习环境更为好一些。在这里简单分享一下。

代码准备

由于使用之后的开发板,并不是相应相应配套的开发板。所以这里只从e203中提取需要的RTL文件。建立一个自己习惯的工作目录,这里简单分享一下,我现在自己用的。FPGA的移植之后会分享给大家,欢迎大家持续关注。
图片alt
·创建目录之后,我们在work目录下,编写makefile。

  1. TESTCASE = ../tb/testcase/rv32ui-p-add
  2. DUMPWAVE = 1
  3. SIM_OPTIONS = -full64 -R +vc +v2k -sverilog -timescale=1ns/1ns -debug_acc+dmptf
  4. FSDB_OPTIONS = +DUMPWAVE=${DUMPWAVE} +define+vcs
  5. all : vcs \
  6. sim \
  7. verdi
  8. run : vcs sim
  9. vcs :
  10. vcs \
  11. ${SIM_OPTIONS} +TESTCASE=${TESTCASE} ${FSDB_OPTIONS} \
  12. -f tblist.f -f filelist.f
  13. sim :
  14. ./simv -l sim.log
  15. verdi :
  16. verdi -sv -f tblist.f -f filelist.f
  17. clean :
  18. rm -rf *~ core csrc simv* vc_hdrs.h ucli.key urg* *.log novas.* *.fsdb* verdiLog 64* DVEfiles *.vpd

· 这里我使用tblist存放tb文件,tb文件还是使用e203原来给的tb文件,filelist存放rtl文件。可以存在同一个list文件,这看个人习惯。
tblist.f内容

  1. +incdir+../tb
  2. ../tb/tb_top.v

filelist.f内容

  1. +incdir+../rtl/core
  2. +incdir+../rtl/perips/apb_i2c
  3. ../rtl/soc/e203_soc_top.v
  4. ../rtl/core/e203_biu.v
  5. ../rtl/core/e203_clkgate.v
  6. ../rtl/core/e203_clk_ctrl.v
  7. ../rtl/core/e203_core.v
  8. ../rtl/core/e203_cpu.v
  9. ../rtl/core/e203_cpu_top.v
  10. ../rtl/core/e203_dtcm_ctrl.v
  11. ../rtl/core/e203_dtcm_ram.v
  12. ../rtl/core/e203_extend_csr.v
  13. ../rtl/core/e203_exu.v
  14. ../rtl/core/e203_exu_alu.v
  15. ../rtl/core/e203_exu_alu_bjp.v
  16. ../rtl/core/e203_exu_alu_csrctrl.v
  17. ../rtl/core/e203_exu_alu_dpath.v
  18. ../rtl/core/e203_exu_alu_lsuagu.v
  19. ../rtl/core/e203_exu_alu_muldiv.v
  20. ../rtl/core/e203_exu_alu_rglr.v
  21. ../rtl/core/e203_exu_branchslv.v
  22. ../rtl/core/e203_exu_commit.v
  23. ../rtl/core/e203_exu_csr.v
  24. ../rtl/core/e203_exu_decode.v
  25. ../rtl/core/e203_exu_disp.v
  26. ../rtl/core/e203_exu_excp.v
  27. ../rtl/core/e203_exu_longpwbck.v
  28. ../rtl/core/e203_exu_nice.v
  29. ../rtl/core/e203_exu_oitf.v
  30. ../rtl/core/e203_exu_regfile.v
  31. ../rtl/core/e203_exu_wbck.v
  32. ../rtl/core/e203_ifu.v
  33. ../rtl/core/e203_ifu_ifetch.v
  34. ../rtl/core/e203_ifu_ift2icb.v
  35. ../rtl/core/e203_ifu_litebpu.v
  36. ../rtl/core/e203_ifu_minidec.v
  37. ../rtl/core/e203_irq_sync.v
  38. ../rtl/core/e203_itcm_ctrl.v
  39. ../rtl/core/e203_itcm_ram.v
  40. ../rtl/core/e203_lsu.v
  41. ../rtl/core/e203_lsu_ctrl.v
  42. ../rtl/core/e203_reset_ctrl.v
  43. ../rtl/core/e203_srams.v
  44. ../rtl/debug/sirv_debug_module.v
  45. ../rtl/debug/sirv_debug_ram.v
  46. ../rtl/debug/sirv_debug_rom.v
  47. ../rtl/debug/sirv_jtag_dtm.v
  48. ../rtl/debug/sirv_debug_csr.v
  49. ../rtl/fab/sirv_icb1to16_bus.v
  50. ../rtl/fab/sirv_icb1to2_bus.v
  51. ../rtl/fab/sirv_icb1to8_bus.v
  52. ../rtl/general/sirv_1cyc_sram_ctrl.v
  53. ../rtl/general/sirv_gnrl_bufs.v
  54. ../rtl/general/sirv_gnrl_dffs.v
  55. ../rtl/general/sirv_gnrl_icbs.v
  56. ../rtl/general/sirv_gnrl_ram.v
  57. ../rtl/general/sirv_gnrl_xchecker.v
  58. ../rtl/general/sirv_sim_ram.v
  59. ../rtl/general/sirv_sram_icb_ctrl.v
  60. ../rtl/mems/sirv_mrom.v
  61. ../rtl/mems/sirv_mrom_top.v
  62. ../rtl/perips/apb_adv_timer/adv_timer_apb_if.v
  63. ../rtl/perips/apb_adv_timer/apb_adv_timer.v
  64. ../rtl/perips/apb_adv_timer/comparator.v
  65. ../rtl/perips/apb_adv_timer/input_stage.v
  66. ../rtl/perips/apb_adv_timer/prescaler.v
  67. ../rtl/perips/apb_adv_timer/timer_cntrl.v
  68. ../rtl/perips/apb_adv_timer/timer_module.v
  69. ../rtl/perips/apb_adv_timer/up_down_counter.v
  70. ../rtl/perips/apb_uart/apb_uart.v
  71. ../rtl/perips/apb_uart/io_generic_fifo.v
  72. ../rtl/perips/apb_uart/uart_interrupt.v
  73. ../rtl/perips/apb_uart/uart_rx.v
  74. ../rtl/perips/apb_uart/uart_tx.v
  75. ../rtl/perips/apb_gpio/apb_gpio.v
  76. ../rtl/perips/apb_i2c/apb_i2c.v
  77. ../rtl/perips/apb_i2c/i2c_master_bit_ctrl.v
  78. ../rtl/perips/apb_i2c/i2c_master_byte_ctrl.v
  79. ../rtl/perips/apb_spi_master/apb_spi_master.v
  80. ../rtl/perips/apb_spi_master/spi_master_apb_if.v
  81. ../rtl/perips/apb_spi_master/spi_master_clkgen.v
  82. ../rtl/perips/apb_spi_master/spi_master_controller.v
  83. ../rtl/perips/apb_spi_master/spi_master_fifo.v
  84. ../rtl/perips/apb_spi_master/spi_master_rx.v
  85. ../rtl/perips/apb_spi_master/spi_master_tx.v
  86. ../rtl/perips/sirv_aon.v
  87. ../rtl/perips/sirv_aon_lclkgen_regs.v
  88. ../rtl/perips/sirv_aon_porrst.v
  89. ../rtl/perips/sirv_aon_top.v
  90. ../rtl/perips/sirv_aon_wrapper.v
  91. ../rtl/perips/sirv_AsyncResetReg.v
  92. ../rtl/perips/sirv_AsyncResetRegVec.v
  93. ../rtl/perips/sirv_AsyncResetRegVec_1.v
  94. ../rtl/perips/sirv_AsyncResetRegVec_129.v
  95. ../rtl/perips/sirv_AsyncResetRegVec_36.v
  96. ../rtl/perips/sirv_clint.v
  97. ../rtl/perips/sirv_clint_top.v
  98. ../rtl/perips/sirv_DeglitchShiftRegister.v
  99. ../rtl/perips/sirv_expl_axi_slv.v
  100. ../rtl/perips/sirv_flash_qspi.v
  101. ../rtl/perips/sirv_flash_qspi_top.v
  102. ../rtl/perips/sirv_hclkgen_regs.v
  103. ../rtl/perips/sirv_jtaggpioport.v
  104. ../rtl/perips/sirv_LevelGateway.v
  105. ../rtl/perips/sirv_plic_man.v
  106. ../rtl/perips/sirv_plic_top.v
  107. ../rtl/perips/sirv_pmu.v
  108. ../rtl/perips/sirv_pmu_core.v
  109. ../rtl/perips/sirv_qspi_arbiter.v
  110. ../rtl/perips/sirv_qspi_fifo.v
  111. ../rtl/perips/sirv_qspi_media.v
  112. ../rtl/perips/sirv_qspi_physical.v
  113. ../rtl/perips/sirv_queue.v
  114. ../rtl/perips/sirv_queue_1.v
  115. ../rtl/perips/sirv_repeater_6.v
  116. ../rtl/perips/sirv_ResetCatchAndSync.v
  117. ../rtl/perips/sirv_ResetCatchAndSync_2.v
  118. ../rtl/perips/sirv_rtc.v
  119. ../rtl/perips/sirv_spi_flashmap.v
  120. ../rtl/perips/sirv_tlfragmenter_qspi_1.v
  121. ../rtl/perips/sirv_tlwidthwidget_qspi.v
  122. ../rtl/perips/sirv_tl_repeater_5.v
  123. ../rtl/perips/sirv_wdog.v
  124. ../rtl/subsys/e203_subsys_clint.v
  125. ../rtl/subsys/e203_subsys_gfcm.v
  126. ../rtl/subsys/e203_subsys_hclkgen.v
  127. ../rtl/subsys/e203_subsys_hclkgen_rstsync.v
  128. ../rtl/subsys/e203_subsys_main.v
  129. ../rtl/subsys/e203_subsys_mems.v
  130. ../rtl/subsys/e203_subsys_nice_core.v
  131. ../rtl/subsys/e203_subsys_perips.v
  132. ../rtl/subsys/e203_subsys_plic.v
  133. ../rtl/subsys/e203_subsys_pll.v
  134. ../rtl/subsys/e203_subsys_pllclkdiv.v
  135. ../rtl/subsys/e203_subsys_top.v

· 同时TB中使用\$value\$plusargs(“xxx=%d”,xxx)语句,从外界传递参数。所以我们可以从,在makefile中设置具体TESTCASE的testcase的存放的路径,这里我们使用rv32ui-p-add.verilog,DUMPWAVE设置为1时,同时预编译VCS时,可以dump对应的.fsdb波形文件。

· 如此,我们使用make命令就可以执行具体仿真操作了,make verdi打开verdi,make run开始编译与仿真。

如果问题,欢迎讨论。

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