从OpenCores网站下了 wb_lpc，添加进e203,寄存器读写都不行，一读就挂死了。

后来照着sirv_gnrl_icb32towishb8改了一个支持32位数据的，也一样的效果。

请过来人有空指点一二，非常感谢

在e203_subsys_perips.v中增加的内容如下：

  wire plc0_icb_cmd_valid;

  wire plc0_icb_cmd_ready;

  wire [31:0] plc0_icb_cmd_addr;

  wire plc0_icb_cmd_read;

  wire [31:0] plc0_icb_cmd_wdata;

  wire [3:0] plc0_icb_cmd_wmask;

  wire plc0_icb_rsp_valid;

  wire plc0_icb_rsp_ready;

  wire [31:0] plc0_icb_rsp_rdata;

  wire plc0_icb_rsp_err;

  wire [31:0] plc0_wishbone_addr; // lower address bits

  wire [31:0] plc0_wishbone_dat_write; // databus input

  wire [31:0] plc0_wishbone_dat_read; // databus output

  wire plc0_wishbone_write_en; // write enable input

  wire plc0_wishbone_stb; // stobe/core select signal

  wire plc0_wishbone_cyc; // valid bus cycle input

  wire plc0_wishbone_ack; // bus cycle acknowledge output

//following three signal is needed by wb_lpc_periph, not but supported by sirv_gnrl_icb32towishb

  wire [3:0] plc0_wishbone_sel;

  wire [1:0] plc0_wishbone_tga;

  wire plc0_wishbone_err;

//for LPC pins signal

  wire iopads_plc0_frame_oen;

  wire iopads_plc0_lad_output_oen;

  wire [3:0] iopads_plc0_lad_o_oen;

  wire iopads_plc0_frame;

  wire iopads_plc0_lad_output_en;

  wire [3:0] iopads_plc0_lad_i;

  wire [3:0] iopads_plc0_lad_o;

    .o15_icb_enable (1'b1),

    .o15_icb_cmd_valid (plc0_icb_cmd_valid),

    .o15_icb_cmd_ready (plc0_icb_cmd_ready),

    .o15_icb_cmd_addr (plc0_icb_cmd_addr),

    .o15_icb_cmd_read (plc0_icb_cmd_read),

    .o15_icb_cmd_wdata (plc0_icb_cmd_wdata),

    .o15_icb_cmd_wmask (plc0_icb_cmd_wmask),

    .o15_icb_cmd_lock (),

    .o15_icb_cmd_excl (),

    .o15_icb_cmd_size (),

    .o15_icb_cmd_burst (),

    .o15_icb_cmd_beat (),

    .o15_icb_rsp_valid (plc0_icb_rsp_valid),

    .o15_icb_rsp_ready (plc0_icb_rsp_ready),

    .o15_icb_rsp_err (plc0_icb_rsp_err),

    .o15_icb_rsp_excl_ok(1'b0),

    .o15_icb_rsp_rdata (plc0_icb_rsp_rdata),

sirv_gnrl_icb32towishb32 # (

  .AW (32)

) lpc0_icbtowishon_bus (

  .i_icb_cmd_valid (plc0_icb_cmd_valid),

  .i_icb_cmd_ready (plc0_icb_cmd_ready),

  .i_icb_cmd_read (plc0_icb_cmd_read),

  .i_icb_cmd_addr (plc0_icb_cmd_addr),

  .i_icb_cmd_wdata (plc0_icb_cmd_wdata),

  .i_icb_cmd_size (),

  .i_icb_rsp_valid (plc0_icb_rsp_valid),

  .i_icb_rsp_ready (plc0_icb_rsp_ready),

  .i_icb_rsp_err (plc0_icb_rsp_err),

  .i_icb_rsp_rdata (plc0_icb_rsp_rdata),

  .wb_adr (plc0_wishbone_addr), // lower address bits

  .wb_dat_w (plc0_wishbone_dat_write), // databus input

  .wb_dat_r (plc0_wishbone_dat_read), // databus output

  .wb_we (plc0_wishbone_dat_write_en), // write enable input

  .wb_stb (plc0_wishbone_dat_stb), // stobe/core select signal

  .wb_cyc (plc0_wishbone_dat_cyc), // valid bus cycle input

  .wb_ack (plc0_wishbone_dat_ack), // bus cycle acknowledge output

 .clk (clk ),

 .rst_n (bus_rst_n)

  );

wb_lpc_periph plc0_device(

 .clk_i(clk),

 .nrst_i(bus_rst_n),

 .wbm_adr_o(plc0_wishbone_addr),

 .wbm_dat_o(plc0_wishbone_dat_write),

 .wbm_dat_i(plc0_wishbone_dat_read),

 .wbm_sel_o(plc0_wishbone_sel),

 .wbm_tga_o(plc0_wishbone_tga),

 .wbm_we_o(plc0_wishbone_dat_write_en),

 .wbm_stb_o(plc0_wishbone_dat_stb),

 .wbm_cyc_o(plc0_wishbone_dat_cyc),

 .wbm_ack_i(plc0_wishbone_dat_ack),

 .wbm_err_i(plc0_wishbone_err),

 .lframe_i(iopads_plc0_frame),

 .lad_i(iopads_plc0_lad_i),

 .lad_o(iopads_plc0_lad_o),

 .lad_oe(iopads_plc0_lad_output_en)

);

sirv_gnrl_icbs.v 中增加的内容：

module sirv_gnrl_icb32towishb32 # (

  parameter AW = 32

) (

  input i_icb_cmd_valid,

  output i_icb_cmd_ready,

  input [1-1:0] i_icb_cmd_read,

  input [31:0] i_icb_cmd_addr,

  input [31:0] i_icb_cmd_wdata,

  input [1:0] i_icb_cmd_size,

  output i_icb_rsp_valid,

  input i_icb_rsp_ready,

  output i_icb_rsp_err,

  output [31:0] i_icb_rsp_rdata,

  // The 32bits wishbone slave (e.g., I2C) must be accessed by load/store byte instructions

  output [31:0] wb_adr, // lower address bits

  output [31:0] wb_dat_w, // databus input

  input [31:0] wb_dat_r, // databus output

  output wb_we, // write enable input

  output wb_stb, // stobe/core select signal

  output wb_cyc, // valid bus cycle input

  input wb_ack, // bus cycle acknowledge output

  input clk,

  input rst_n

  );

  assign wb_adr = i_icb_cmd_addr;

  assign wb_we = ~i_icb_cmd_read;

  // The 32bits bus to 8bits bus remapping

  assign wb_dat_w = i_icb_cmd_wdata;

  //wire [32-1:0] wb_dat_r_remap = {24'b0,wb_dat_r} << {i_icb_cmd_addr[1:0],3'b0};

  // Since the Wishbone reponse channel does not have handhake scheme, but the

  // ICB have, so the response may not be accepted by the upstream master

  // So in order to make sure the functionality is correct, we must put

  // a reponse bypass-buffer here, to always be able to accept response from wishbone

  //

  sirv_gnrl_fifo # (

   .CUT_READY (1),

   .MSKO (0),

   .DP(1),

   .DW(32)

  ) u_rsp_fifo(

    .i_vld(wb_ack),

    .i_rdy(),

    .i_dat(wb_dat_r),

    .o_vld(i_icb_rsp_valid),

    .o_rdy(i_icb_rsp_ready),

    .o_dat(i_icb_rsp_rdata),

    .clk (clk ),

    .rst_n(rst_n)

   );

  // We only initiate the reqeust when the response buffer is empty, to make

  // sure when the response back from wishbone we can alway be able to

  // accept it

  assign wb_stb = (~i_icb_rsp_valid) & i_icb_cmd_valid;

  assign wb_cyc = (~i_icb_rsp_valid) & i_icb_cmd_valid;

  assign i_icb_cmd_ready = (~i_icb_rsp_valid) & wb_ack;

  assign i_icb_rsp_err = 1'b0;// Wishbone have no error response

endmodule