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【求助】 [求助]非官方FPGA开发板,四线JTAG下载程序失败,请问如何解决?

发表于 开源蜂鸟E203 2023-02-12 14:41:53
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开发板:正点原子达芬奇Pro开发板FPGA Artix-7 XC7A100T
调试器:Sipeed USB-JTAG/TTL RISC-V调试器

OpenOCD报错如下:

Open On-Chip Debugger 0.11.0+dev-01897-gc8fc2a168 (2022-04-01-04:46)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter speed' not 'adapter_khz'
DEPRECATED! use 'adapter driver' not 'interface'
Info : Using libusb driver
Info : clock speed 1000 kHz
Info : JTAG tap: riscv.cpu tap/device found: 0x1e200a6d (mfg: 0x536 (Nuclei System Technology Co Ltd), part: 0xe200, ver: 0x1)
Info : TAP auto0.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto1.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto2.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto3.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto4.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto5.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto6.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto7.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto8.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto9.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto10.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto11.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto12.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto13.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto14.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto15.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto16.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto17.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto18.tap does not have valid IDCODE (idcode=0x0)
Info : TAP auto19.tap does not have valid IDCODE (idcode=0x0)
Warn : Unexpected idcode after end of chain: 52 0x00000000
Warn : Unexpected idcode after end of chain: 84 0xfe000000
Error: double-check your JTAG setup (interface, speed, ...)
Error: Trying to use configured scan chain anyway...
Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 2 -expected-id 0x00000000"
Error: auto0.tap: IR capture error; saw 0x0000 not 0x0001
Warn : Bypassing JTAG setup events due to errors
Error: Unsupported DTM version 14. (dtmcontrol=0xffe)
Warn : target riscv.cpu examination failed
Info : starting gdb server for riscv.cpu on 3333
Info : Listening on port 3333 for gdb connections
Error: Target not examined yet
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用户评论 (10)
  • 胡灿

    2023-02-15 09:43:45 胡灿 1#

    那就把OpenOCD的详细log打印出来看看吧。

    用两条命令在两个terminal里面来跑,make run_openocd先运行OpenOCD,要加上-D参数就会打印详细log,openOCD起来后再换个terminal运行GDB,make run_gdb,具体的命令如何运行看看Hbird SDK如何使用。

  • MicrooGRIT

    2023-02-14 11:20:01 MicrooGRIT 2#

    MicrooGRIT

    去掉这个约束还是同样的情况

    我的TOP也是参考您的官方例程

  • MicrooGRIT

    2023-02-14 11:16:09 MicrooGRIT 3#

    MicrooGRIT

    本来是没有加TCK时钟约束的,后来觉得是一个时钟的输入,所以需要约束一下,我修改后再试一下,谢谢胡先生!

    去掉这个约束还是同样的情况

  • MicrooGRIT

    2023-02-14 11:05:02 MicrooGRIT 4#

    胡灿

    为何JTAG TCK上还接了固定时钟呢,这个是由调试器来产生的信号。

    参考下蜂鸟自身的约束文件和FPGA TOP吧

    本来是没有加TCK时钟约束的,后来觉得是一个时钟的输入,所以需要约束一下,我修改后再试一下,谢谢胡先生!

  • 胡灿

    2023-02-14 11:02:22 胡灿 5#

    MicrooGRIT

    谢谢胡先生的回复!

    我的约束如下:

    ```

    #------------------------------系统时钟和复位-----------------------------------

    create_clock -period 20.000 -name sys_clk [get_ports sys_clk]

    set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS15} [get_ports sys_clk]

    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sys_clk]

    set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS15} [get_ports mcu_rst]


    create_clock -period 1000.000 -name jtag_clk [get_ports mcu_TCK]



    set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks CLK_O_8M388_PLL]

                                     -group [get_clocks -include_generated_clocks CLK_O_16M_PLL]

                                     -group [get_clocks -include_generated_clocks jtag_clk]

    #-----------------------------------UART----------------------------------------

    set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS33} [get_ports uart0_rxd]

    set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports uart0_txd]

    #-----------------------------------MCU_JTAG----------------------------------------

    set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports mcu_TCK]

    set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports mcu_TDO]

    set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports mcu_TMS]

    set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports mcu_TDI]

    set_property KEEPER true [get_ports mcu_TMS]

    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IOBUF_jtag_TCK/O]

    #---------------------------------QSPI_FLASH----------------------------------------

    set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports qspi0_cs]

    set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS33} [get_ports qspi0_sck]

    set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS33} [get_ports qspi0_dq[0]]

    set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33} [get_ports qspi0_dq[1]]

    set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS33} [get_ports qspi0_dq[2]]

    set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports qspi0_dq[3]]

    ```


    为何JTAG TCK上还接了固定时钟呢,这个是由调试器来产生的信号。

    参考下蜂鸟自身的约束文件和FPGA TOP吧

  • MicrooGRIT

    2023-02-14 10:56:10 MicrooGRIT 6#

    胡灿

    这个看上去是JTAG除了检测出蜂鸟的内核外,还在往后扫描,读到的东西又不对。

    检测一下硬件架构和管脚约束吧

    谢谢胡先生的回复!

    我的约束如下:

    ```

    #------------------------------系统时钟和复位-----------------------------------

    create_clock -period 20.000 -name sys_clk [get_ports sys_clk]

    set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS15} [get_ports sys_clk]

    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sys_clk]

    set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS15} [get_ports mcu_rst]


    create_clock -period 1000.000 -name jtag_clk [get_ports mcu_TCK]



    set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks CLK_O_8M388_PLL]

                                     -group [get_clocks -include_generated_clocks CLK_O_16M_PLL]

                                     -group [get_clocks -include_generated_clocks jtag_clk]

    #-----------------------------------UART----------------------------------------

    set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS33} [get_ports uart0_rxd]

    set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports uart0_txd]

    #-----------------------------------MCU_JTAG----------------------------------------

    set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports mcu_TCK]

    set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports mcu_TDO]

    set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports mcu_TMS]

    set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports mcu_TDI]

    set_property KEEPER true [get_ports mcu_TMS]

    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IOBUF_jtag_TCK/O]

    #---------------------------------QSPI_FLASH----------------------------------------

    set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33} [get_ports qspi0_cs]

    set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS33} [get_ports qspi0_sck]

    set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS33} [get_ports qspi0_dq[0]]

    set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS33} [get_ports qspi0_dq[1]]

    set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS33} [get_ports qspi0_dq[2]]

    set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports qspi0_dq[3]]

    ```


  • 胡灿

    2023-02-14 10:52:26 胡灿 7#

    这个看上去是JTAG除了检测出蜂鸟的内核外,还在往后扫描,读到的东西又不对。

    检测一下硬件架构和管脚约束吧

  • MicrooGRIT

    2023-02-13 18:20:45 MicrooGRIT 8#

    wonder

    可以参考: https://www.riscv-mcu.com/community-topic-id-1014.html

    谢谢您的回复!

    我之前看过这个帖子了,也跟着这个做了,还是没效果

  • wonder

    2023-02-13 16:57:22 wonder 9#

    可以参考: https://www.riscv-mcu.com/community-topic-id-1014.html

  • MicrooGRIT

    2023-02-12 14:44:35 MicrooGRIT 10#

    已修改为内部ROM启动,并注释了*.cfg文件中的Flash相关代码

MicrooGRIT

MicrooGRIT 实名认证

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