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static void system_clock_108m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
#ifdef RTThread_DevBoard
/* enable IRC8MEN */
RCU_CTL |= RCU_CTL_IRC8MEN;
/* wait until IRC8MEN is stable or the startup time is longer than
* IRC8M_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_IRC8MSTB);
} while ((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
/* if fail */
if (0U == (RCU_CTL & RCU_CTL_IRC8MSTB)) {
while (1) {
}
}
#else
/* enable HXTAL */
RCU_CTL |= RCU_CTL_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than
* HXTAL_STARTUP_TIMEOUT */
do {
timeout++;
stab_flag = (RCU_CTL & RCU_CTL_HXTALSTB);
} while ((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if (0U == (RCU_CTL & RCU_CTL_HXTALSTB)) {
while (1) {
}
}
/* HXTAL is stable */
#endif
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB/1 */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB/2 */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV2;
/* CK_PLL = (CK_PREDIV0) * 27 = 108 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLMF | RCU_CFG0_PLLMF_4);
#ifdef RTThread_DevBoard
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL27);
#else
RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL27);
#endif
#ifdef RTThread_DevBoard
#else
if (HXTAL_VALUE == 25000000) {
/* CK_PREDIV0 = (CK_HXTAL)/5 *8 /10 = 4 MHz */
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF |
RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PREDV0SRC_CKPLL1 | RCU_PREDV1_DIV5 | RCU_PLL1_MUL8 |
RCU_PREDV0_DIV10);
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {
}
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL2EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {
}
} else if (HXTAL_VALUE == 8000000) {
RCU_CFG1 &= ~(RCU_CFG1_PREDV0SEL | RCU_CFG1_PREDV1 | RCU_CFG1_PLL1MF |
RCU_CFG1_PREDV0);
RCU_CFG1 |= (RCU_PREDV0SRC_HXTAL | RCU_PREDV0_DIV2 | RCU_PREDV1_DIV2 |
RCU_PLL1_MUL20 | RCU_PLL2_MUL20);
/* enable PLL1 */
RCU_CTL |= RCU_CTL_PLL1EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL1STB)) {
}
/* enable PLL2 */
RCU_CTL |= RCU_CTL_PLL2EN;
/* wait till PLL1 is ready */
while (0U == (RCU_CTL & RCU_CTL_PLL2STB)) {
}
}
#endif
/* enable PLL */
RCU_CTL |= RCU_CTL_PLLEN;
/* wait until PLL is stable */
while (0U == (RCU_CTL & RCU_CTL_PLLSTB)) {
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while (0U == (RCU_CFG0 & RCU_SCSS_PLL)) {
}
}
#ifdef RTThread_DevBoard
/* RT-Thread board UART com port */
#define GD32_COM0 USART0
#define GD32_COM_CLK RCU_USART0
#define GD32_COM_TX_PIN GPIO_PIN_9
#define GD32_COM_RX_PIN GPIO_PIN_10
#define GD32_COM_TX_GPIO_PORT GPIOA
#define GD32_COM_RX_GPIO_PORT GPIOA
#define GD32_COM_TX_GPIO_CLK RCU_GPIOA
#define GD32_COM_RX_GPIO_CLK RCU_GPIOA
#else
/* rvstar board UART com port */
#define GD32_COM0 UART4
#define GD32_COM_CLK RCU_UART4
#define GD32_COM_TX_PIN GPIO_PIN_12
#define GD32_COM_RX_PIN GPIO_PIN_2
#define GD32_COM_TX_GPIO_PORT GPIOC
#define GD32_COM_RX_GPIO_PORT GPIOD
#define GD32_COM_TX_GPIO_CLK RCU_GPIOC
#define GD32_COM_RX_GPIO_CLK RCU_GPIOD
#endif