团队名称：能做队 报名编号：CICC1441

一：生成程序的bin文件

方法一：直接用NucleiStudio生成程序的bin文件
方法二：命令行执行，例如：riscv-nuclei-elf-objcopy -O binary hello_test.elf hello_test.bin
其中.elf文件在工程目录下可以找到。

二：用python解析bin文件，转化为verilog的initial语块,以.txt格式存储

本人对python只有入门级的了解，这里提供一个很粗糙的模板：(以itcm的位宽为64位为例)
#读取bin文件
name = “hello_test”
filepath = name+”.bin”
targetpath = name+”.data”
target = open(targetpath, “w”)
binfile = open(filepath, ‘rb’)
i = 0
ch = binfile.read(1)
while ch:
data = ord(ch)
target.write (“%02X” %(data))
if i % 8 == 7:
target.write (“\n”)
i = i + 1
ch = binfile.read(1)
binfile.close()

#转为verilog的initial语句
filepath = name+”.data”
targetpath = name+”.txt”
target = open(targetpath, “w”)
datafile = open(filepath, ‘r’)
i = 0
ch1 = datafile.read(1)
ch2 = datafile.read(1)
ch3 = datafile.read(1)
ch4 = datafile.read(1)
ch5 = datafile.read(1)
ch6 = datafile.read(1)
ch7 = datafile.read(1)
ch8 = datafile.read(1)
ch9 = datafile.read(1)
ch10 = datafile.read(1)
ch11 = datafile.read(1)
ch12 = datafile.read(1)
ch13 = datafile.read(1)
ch14 = datafile.read(1)
ch15 = datafile.read(1)
ch16 = datafile.read(1)

target.write(“initial begin”)
target.write(“\n”)
while ch16:
target.write(“ mem_r[%d]=64’h” %i)
target.write (ch15)
target.write (ch16)
target.write (ch13)
target.write (ch14)
target.write (ch11)
target.write (ch12)
target.write (ch9)
target.write (ch10)
target.write (ch7)
target.write (ch8)
target.write (ch5)
target.write (ch6)
target.write (ch3)
target.write (ch4)
target.write (ch1)
target.write (ch2)
target.write (“;”)
target.write(“\n”)
i=i+1
ch = datafile.read(1)
ch1 = datafile.read(1)
ch2 = datafile.read(1)
ch3 = datafile.read(1)
ch4 = datafile.read(1)
ch5 = datafile.read(1)
ch6 = datafile.read(1)
ch7 = datafile.read(1)
ch8 = datafile.read(1)
ch9 = datafile.read(1)
ch10 = datafile.read(1)
ch11 = datafile.read(1)
ch12 = datafile.read(1)
ch13 = datafile.read(1)
ch14 = datafile.read(1)
ch15 = datafile.read(1)
ch16 = datafile.read(1)
target.write (“end\n”)
target.close()
datafile.close()

三：将生成的*.txt内的内容复制进itcm的sram中（本质上为初始化sram的内容）

可以直接复制该内容到sirv_sim_ram.v文件里，但这是很不好的做法，因为不止一个上层模块会调用该模块，最好重写一份sirv_sim_ram.v。（或者直接换个模块名就好了，内容不变）

四：顶层模块选择从room启动

e203_soc_top dut
(
…
.io_pads_bootrom_n_i_ival (1’b0),
.io_pads_dbgmode0_n_i_ival (1’b1),
.io_pads_dbgmode1_n_i_ival (1’b1),
.io_pads_dbgmode2_n_i_ival (1’b1)
);